********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Dec 22, 2014
*ECN S14-2165, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si8457DB  D G S 
M1 3 GX S S PMOS W= 3210000u L= 0.3u 
M2 S GX S D NMOS W= 3210000u L= 0.41u
R1 D 3 1.1704e-2 1.9918e-03 0 
CGS GX S 5.3993e-10 
CGD GX D 5.075e-12 
RG G GY 16 
RTCV 100 S 1e6 -1.008e-04 -1.182e-06 
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 3210000u 
**************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 2e-8 
+ RS = 0 KP = 7.2707e-06 NSUB = 3.010e+15 
+ KAPPA = 1.095e-04 NFS = 9.695e+11 
+ LD = 0 IS = 0 TPG = -1 CAPOP = 12 ) 
*************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 2e-8 
+NSUB = 1.916e+17 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-08 TREF = 25 BV = 13 
+RS = 3.594e-02 N = 1.777e+00 IS = 2.692e-07 
+EG = 6.802e-01 XTI = 9.919e+00 TRS = 1.000e-05 
+CJO = 8.159e-11 VJ = 3.638e-01 M = 3.696e-01 ) 
.ENDS 
